FPGA Logic Analyzer Add-Ons

2.5 - 5.0V Input Stage Using TI SN74ALVTH16244

This add-on was contributed by Richard T. Stofer. The text below ist mostly taken from his e-mail. The board has not yet been tested over the full frequency range of the analyzer.


In the top right corner there is a set of pin rows for a 40 pin right angle header that will plug in to port B1. Just below and to the right are two 0805 capacitor layouts. One is a 10µF tantalum and the other a 0.1µF ceramic. Along the center of the layout are four more capacitors. The one on the far left is a 10µF tantalum and the remaining three are 0.1µF ceramic. The three ICs are TI SN74ALVTH16244 (SSOP).

Now to the connectors along the lower edge: the upper pair is a female 40 pin header while the lower rows are pin headers.  The female header allows to connect to prototype boards with male-male jumpers. The next row is entirely ground connections and is labeled on both ends. The next two rows are signals and the first signal is next to the pin marked '1' (on the right end) and the next signal is adjacent to '2'. The signals continue along this pair of rows, extending left, until signals 31 and 32. Finally, the lower row of pins are all grounded.

Over at the left column of pins the clock output is routed to all 4 ungrounded pins and labeled.

Download Layout (PDF and ExpressPCB)

Joel Simpson (Thu, 19 Jun 2008):
Would this product work for level shifting.

A bit unwieldy, but much less expensive than having a board made up.

-sorry for the duplicate comment on the FAQ.
Micha (Thu, 3 Jul 2008):
@Joel Simpson:
It appears your link stopped working.
Andreas (Sat, 31 Jan 2009):
The PDFs are not usable because the silkscreen has not been switched off. The border of the ICs is shortening all the traces.
nall (Tue, 28 Apr 2009):
I think he means this link:

nall (Tue, 28 Apr 2009):
Oh weird. The comment posting eats an underscore. There should be an underscore between product and info

nuess0r (Mon, 7 Jun 2010):
I did a new version of input stage addon. I used gEDA. Files and documentations is here: