If you don't want to be restricted to measuring 3,3V signals, you need a level shifter. Such a device can be built using 74LVC4245 or 74ALVTH162244.
How do I connect the signal wires?
Inputs 0-31 can be found on Connector B1 Pin 4-35 in ascending order. Ground is Pin 1. External clock connects to A2 Pin 35. The internal sampling clock is outputted on Connector B1 Pin 40.
How do I set the transfer rate on the board?
This is done using the switches SW1 and SW0. The proper switch settings can be found in the Capture Dialog of the Client. (In Parenthesis behind the transfer rate. H means up.)
How are the LEDs of the 7 segment display mapped to the channels?
Every digit including the dot shows 8 channels. Mapping of digits to channels from left to right: 31-24, 23-16, 15-8, 7-0. Within each digit the channels are ordered (ascending) as follows: The outer LEDs of a digit - starting with the top horizontal bar - in clockwise direction, followed by the middle bar, followed by the dot.
What does the message "Error while invoking apllication:null" mean?
The same as "NoClassDefFoundError: gnu/io/CommPortIdentifier". See below.
What does the message "NoClassDefFoundError: gnu/io/CommPortIdentifier" mean?
The RXTX library is not installed correctly. Ready to use binaries for Windows, Linux and Mac are available here. The included INSTALL file describes which file goes where on which platform. The matching download for other systems can be found on the RXTX home page
How do I install PgsLookAndFeel?
The zip archive contains "PgsLookAndFeel.jar". This files is copied into the ext directory of the JRE. (In Linux the path could be"/usr/lib/java/jre/lib/ext") In case it does not exist, create the file "swing.properties" in the lib directory of the JRE. Add the following line to this file: swing.defaultlaf=com.pagosoft.plaf.PgsLookAndFeel
How do I add the source in ISE WebPack 8.1?
Create a new project for device XC3S200, package ft256 and speed -4 and add all VHD files and the UCF file using "Add Source".
Why is the synthesizer reporting a max. clock of 50MHz instead of 100/200Mhz?
The maximum clock frequency displayed when synthesizing is the maximum for the clock signal from the crystal oscillator. This is not the signal that is used for sampling. The frequency is doubled inside the FPGA using a DCM. This gives 100MHz. And the maximum sampling rate of 200MHz is achived using a DDR approach, meaning data is sampled on falling and rising edge of the 100MHz signal.