FPGA Based Logic Analyzer
The outcome of this project is a logic analysator for home use.
The project includes the actual analyzer in VHDL (for Spartan 3 FPGA) and a PC Software for the end user. The design employs a FPGA board that can be obtained easily.
Features
- 16 channels at 200MHz sampling rate
- 32 channels up to 100MHz sampling rate
- state analysis up to 50MHz using external clock
- 256KSamples memory
- noise filter
- complex serial and parallel trigger with four stages
- externally available sampling clock to drive add-ons (like ADCs)
- connects via EIA232/RS232 (works with usb to serial adapters)
- Java based viewing software (see PC Client for details)
- I2C & SPI protocol analysis
Hardware
The device uses a Xilinx Spartan 3 Starter Kit (DO-SPAR3-DK) evaluation board manufactured by Digilent. It features a XC3S200-4 FPGA with 4ns propagation delay and 3840 cells. Onboard are 1MByte of 10ns SRAM and plenty connectors that can be used as signal inputs.
To construct a comparable board from scratch would be a tough task for a home project. Especially the really low price of about USD100 makes it pointless to try to compete with this "mass product". All that remains to be done is to program the FPGA. For an overview of the VHDL code see:
To learn how to communicate with the analyzer read:
Client
A java client is used to access the device from almost any PC with a serial port. The client uses the RXTX library for serial port communications which is available for 34 platforms including Linux, Windows and Solaris.
It has been developed with jdk 1.4.2 but might work with older versions. More information about the client can be found on its page:
License
Files found in the downloadable archives below are released under the GNU GPL.
Downloads
Packages contain all that is needed for PC client, FPGA and tester.
See history for a list of changes between versions
"Official" Version
Logic Analyzer Package v0.8 - Binary (2007-03-03)
Logic Analyzer Package v0.8 - Source (2007-03-03)
User Contributed Versions
These downloads are provided without any testing.
Altera DE2: Experimental Port to Verilog for Altera DE2 Board - Source (2007-05-21)
(Contributed by Kenneth Tsang. Uses external SRAM.)
Altera DE2: Experimental Port to Verilog for Altera DE2 Board - Source (2007-05-21)
(Contributed by Kenneth Tsang. Uses internal M4K SRAM.)
Spartan 3E: Experimental Version for New Spartan 3E Starter Kit - Source (2007-03-08)
(Contributed by Jonas Diemer. Uses internal BRAM with optional RLE.)
Archive
Logic Analyzer Package v0.7 - Source (2006-12-31)
Logic Analyzer Package v0.6 - Source (2006-08-19)
Logic Analyzer Package v0.5 - Source (2006-06-18)
Logic Analyzer Package v0.4 - Source (2006-05-23)
Logic Analyzer Package v0.3 - Source (2006-05-05)
Hello sir
This is Nagarjun here , doing my engineering in National Institute of Engineering ,Mysore. we are been doing implementation of logic analyser using altera de2 board. we have been able to acquire the data from an external digital system and also display it using the signal tap , but our aim is to display the signals using the vga monitor to which input can be fed through the vga out provided in the altera de2 board. its here we are facing problems as we are not able to display 8 channels using the single dac in the altera board, so if u can give us some guide lines or tell us how to go about it will be of great help.
[Edited by Micha: Removed source code as it did take up too much room.]
Seeing your concerns about only having one DAC for the VGA display, you might want to have a look at what a VGA signal looks like for a start. For a very simple solution all you need to do is implement a line counter and draw each signal in its own line. You might want to draw from RAM so all lines will show the exact same time slot.
Apart from this I can't help you as your issue doesn't really have to do with my project.
Micha,
I cannot thank you enough. I can't really afford a logic analyzer right now, but I did have a digilent board in my stash. I built this, and it works great! I had to recompile the source for my xc3s400 board though.
I hope you don't mind me asking a quick question - what exactly do the triggers do? Are they used to start the capture when, say, channel 3 goes high? Or do they have another use?
Again, thanks a ton!
-jeremy
The source has to be recompiled for all but the XC3S200 device, because the configuration image depends on the number of logic cells.
Yes, the sole purpose of the trigger is to start the capture when certain conditions are met.
In the simplest case the capture starts when all channels where the mask field is checked have the specified values. (1 = checked; 0 = unchecked) If the trigger is in serial mode, the bits apply to the last 32 bits sampled on the configured channel.
Multiple stages can be used to configure more complex scenarios where multiple conditions have to be met over time before the capture starts.
Hi,
I just wanted to make quick question about the VHDL code in SRAM block. I ve tried the code but when I simulated it in modelsim the address counter wasnt working. I dont know why. I thought that the simulator cannot guess which one of the two process to run first.
Thanks
You mentioned that you used a digilent board. I searched their website and the only Match I found according to your specifications is Nexys. It seems that this board is deprecated. Does your code work with Nexys-2 ?
Thanks! This is really an amazing piece of software!
@Spyros:
Only one of the processes has an impact on the address counter. There should be no dependencies between the two. Are you sure you applied the proper read/write signals?
@bazzoola:
Check the digilent site for the "The Spartan-3 Starter Board". Its in the list below the Nexys-2.
I would not recomment the Nexys-2 as it uses Dynamic RAM for which there is no support in the analyzer yet. (It is uncertain if there ever will be full support, because DRAM is usually a lot slower than the SRAM.)
Hi, anyone tried the Spartan 3E Starter Kit version with success? The client can't connect to the board. I'm using a RS232 to USB converter, could this be a problem?
How do I use this? Do I just add the sources inside the fpga folder into my project and generate the file?
Im geting error with synthesizing =( Im using the Spartan 3E starter kit
Hi Micha,
What do you think about the SPARTAN 3A Board ? Thats a new development board, which just costs around 40 US$. If an adaption to that board would be possible, it would be perfect.
Any ideas?
cheers,
Daniel
@nagio:
I'm using a RS232 to USB converter myself without any problems. Have you tried lowering the transfer rate?
@Zhane:
Did you adjust the device settings for your board? Did you add the ucf file too? What is the error message you are getting?
@Daniel:
This board has the same problem as all the newer ones: it uses slow (DDR) SDRAM instead of fast SRAM. There is no SDRAM support built into the analyzer, so you would be limited to the FPGA internal BRAM.
Apart from this I cannot tell you if the 3E version (which uses BRAM) will work on a 3A board.
yes, but the result is always the same. I've tested the RS232 connection between the board and the laptop using the examples on xilinx website and they works so I don't think the problem lies in the converter.
Unfortunately I do not have a 3E myself, but it works for others. You might want to try to connect the on-board LEDs to input channels or bits of registers (like trigger mask or speed) to see if the analyzer is running at all.
In the offical analyzer package for the regular starter kit the serial rx & tx are also connected to LEDs. If thats not the case for the 3E by default, you should connect those too to see if there is any activity.
Also make sure you are using the client that comes with the modified package, because the regular client does not support RLE.
Dear Michael Poppitz,
I tried Your logic analyzer with my newly arrived Spartan3E Starter Board,
it works really fine (WebPack 9.2i). Congratulations for your clearly structured sources.
There are just some little problems left:
1. I am using serial port DCE with a USB-Serial Converter (DA-70145- Rev 2.0 from Digitus).
On my desktop PC it installed as a "Motorola Comp Modem" (USB-Serial Controller) and everything works fine.
On my Laptop PC it installed as a "Prolific USB-to-Serial Comm Port" (USB-Serial Controller) and it works fine with Hyperterm
and my FPGA UARTS but not with your Client. Baudrate, Handshale etc is double checked. - Any Suggestion for debugging?
(Device Id returned is 0x0; device not found)
2. Are there any works done for a glitch detector? I think I would like to have one.
3. Do you know if anybody has written a User Manual for your analyzer?
Yours
DI Hermann Dum
HTBL Hollabrunn
Hi,
i have a Digitus (includes Prolific chip) USB-RS232 converter, too. It works fine but not with the original MS drivers. So, how to get it running: goto http://www.ftdichip.com/Resources/Utilities.htm and load the "Microsoft USBView" tool. Check with this tool which plXXXX chip is in your USB-RS232 converter. Then goto http://www.prolific.com.tw/eng/Download-2.asp?ID=17 and load the driver for your chipset and install it. Then the converter should work.
regards,
Frank