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FPGA Based Logic Analyzer
The outcome of this project is a logic analysator for home use.
The project includes the actual analyzer in VHDL (for Spartan 3 FPGA) and a PC Software for the end user. The design employs a FPGA board that can be obtained easily.
Features
- 16 channels at 200MHz sampling rate
- 32 channels up to 100MHz sampling rate
- state analysis up to 50MHz using external clock
- 256KSamples memory
- noise filter
- complex serial and parallel trigger with four stages
- externally available sampling clock to drive add-ons (like ADCs)
- connects via EIA232/RS232 (works with usb to serial adapters)
- Java based viewing software (see PC Client for details)
- I2C & SPI protocol analysis
Hardware
The device uses a Xilinx Spartan 3 Starter Kit (DO-SPAR3-DK) evaluation board manufactured by Digilent. It features a XC3S200-4 FPGA with 4ns propagation delay and 3840 cells. Onboard are 1MByte of 10ns SRAM and plenty connectors that can be used as signal inputs.
To construct a comparable board from scratch would be a tough task for a home project. Especially the really low price of about USD100 makes it pointless to try to compete with this "mass product". All that remains to be done is to program the FPGA. For an overview of the VHDL code see:
To learn how to communicate with the analyzer read:
Client
A java client is used to access the device from almost any PC with a serial port. The client uses the RXTX library for serial port communications which is available for 34 platforms including Linux, Windows and Solaris.
It has been developed with jdk 1.4.2 but might work with older versions. More information about the client can be found on its page:
License
Files found in the downloadable archives below are released under the GNU GPL.
Downloads
Packages contain all that is needed for PC client, FPGA and tester.
See history for a list of changes between versions
"Official" Version
Logic Analyzer Package v0.8 - Binary (2007-03-03)
Logic Analyzer Package v0.8 - Source (2007-03-03)
User Contributed Versions
These downloads are provided without any testing.
Altera DE2: Experimental Port to Verilog for Altera DE2 Board - Source (2007-05-21)
(Contributed by Kenneth Tsang. Uses external SRAM.)
Altera DE2: Experimental Port to Verilog for Altera DE2 Board - Source (2007-05-21)
(Contributed by Kenneth Tsang. Uses internal M4K SRAM.)
Spartan 3E: Experimental Version for New Spartan 3E Starter Kit - Source (2007-03-08)
(Contributed by Jonas Diemer. Uses internal BRAM with optional RLE.)
Archive
Logic Analyzer Package v0.7 - Source (2006-12-31)
Logic Analyzer Package v0.6 - Source (2006-08-19)
Logic Analyzer Package v0.5 - Source (2006-06-18)
Logic Analyzer Package v0.4 - Source (2006-05-23)
Logic Analyzer Package v0.3 - Source (2006-05-05)
Comments
Nagarjun (Tue, 6 May 2008):
Hello sir
This is Nagarjun here , doing my engineering in National Institute of Engineering ,Mysore. we are been doing implementation of logic analyser using altera de2 board. we have been able to acquire the data from an external digital system and also display it using the signal tap , but our aim is to display the signals using the vga monitor to which input can be fed through the vga out provided in the altera de2 board. its here we are facing problems as we are not able to display 8 channels using the single dac in the altera board, so if u can give us some guide lines or tell us how to go about it will be of great help.
[Edited by Micha: Removed source code as it did take up too much room.]
Hello sir
This is Nagarjun here , doing my engineering in National Institute of Engineering ,Mysore. we are been doing implementation of logic analyser using altera de2 board. we have been able to acquire the data from an external digital system and also display it using the signal tap , but our aim is to display the signals using the vga monitor to which input can be fed through the vga out provided in the altera de2 board. its here we are facing problems as we are not able to display 8 channels using the single dac in the altera board, so if u can give us some guide lines or tell us how to go about it will be of great help.
[Edited by Micha: Removed source code as it did take up too much room.]
Micha (Tue, 6 May 2008):
Seeing your concerns about only having one DAC for the VGA display, you might want to have a look at what a VGA signal looks like for a start. For a very simple solution all you need to do is implement a line counter and draw each signal in its own line. You might want to draw from RAM so all lines will show the exact same time slot.
Apart from this I can't help you as your issue doesn't really have to do with my project.
Seeing your concerns about only having one DAC for the VGA display, you might want to have a look at what a VGA signal looks like for a start. For a very simple solution all you need to do is implement a line counter and draw each signal in its own line. You might want to draw from RAM so all lines will show the exact same time slot.
Apart from this I can't help you as your issue doesn't really have to do with my project.
jeremy (Fri, 16 May 2008):
Micha,
I cannot thank you enough. I can't really afford a logic analyzer right now, but I did have a digilent board in my stash. I built this, and it works great! I had to recompile the source for my xc3s400 board though.
I hope you don't mind me asking a quick question - what exactly do the triggers do? Are they used to start the capture when, say, channel 3 goes high? Or do they have another use?
Again, thanks a ton!
-jeremy
Micha,
I cannot thank you enough. I can't really afford a logic analyzer right now, but I did have a digilent board in my stash. I built this, and it works great! I had to recompile the source for my xc3s400 board though.
I hope you don't mind me asking a quick question - what exactly do the triggers do? Are they used to start the capture when, say, channel 3 goes high? Or do they have another use?
Again, thanks a ton!
-jeremy
Micha (Sat, 17 May 2008):
The source has to be recompiled for all but the XC3S200 device, because the configuration image depends on the number of logic cells.
Yes, the sole purpose of the trigger is to start the capture when certain conditions are met.
In the simplest case the capture starts when all channels where the mask field is checked have the specified values. (1 = checked; 0 = unchecked) If the trigger is in serial mode, the bits apply to the last 32 bits sampled on the configured channel.
Multiple stages can be used to configure more complex scenarios where multiple conditions have to be met over time before the capture starts.
The source has to be recompiled for all but the XC3S200 device, because the configuration image depends on the number of logic cells.
Yes, the sole purpose of the trigger is to start the capture when certain conditions are met.
In the simplest case the capture starts when all channels where the mask field is checked have the specified values. (1 = checked; 0 = unchecked) If the trigger is in serial mode, the bits apply to the last 32 bits sampled on the configured channel.
Multiple stages can be used to configure more complex scenarios where multiple conditions have to be met over time before the capture starts.
Spyros (Wed, 28 May 2008):
Hi,
I just wanted to make quick question about the VHDL code in SRAM block. I ve tried the code but when I simulated it in modelsim the address counter wasnt working. I dont know why. I thought that the simulator cannot guess which one of the two process to run first.
Thanks
Hi,
I just wanted to make quick question about the VHDL code in SRAM block. I ve tried the code but when I simulated it in modelsim the address counter wasnt working. I dont know why. I thought that the simulator cannot guess which one of the two process to run first.
Thanks
bazzoola (Mon, 9 Jun 2008):
You mentioned that you used a digilent board. I searched their website and the only Match I found according to your specifications is Nexys. It seems that this board is deprecated. Does your code work with Nexys-2 ?
Thanks! This is really an amazing piece of software!
You mentioned that you used a digilent board. I searched their website and the only Match I found according to your specifications is Nexys. It seems that this board is deprecated. Does your code work with Nexys-2 ?
Thanks! This is really an amazing piece of software!
Micha (Thu, 12 Jun 2008):
@Spyros:
Only one of the processes has an impact on the address counter. There should be no dependencies between the two. Are you sure you applied the proper read/write signals?
@bazzoola:
Check the digilent site for the "The Spartan-3 Starter Board". Its in the list below the Nexys-2.
I would not recomment the Nexys-2 as it uses Dynamic RAM for which there is no support in the analyzer yet. (It is uncertain if there ever will be full support, because DRAM is usually a lot slower than the SRAM.)
@Spyros:
Only one of the processes has an impact on the address counter. There should be no dependencies between the two. Are you sure you applied the proper read/write signals?
@bazzoola:
Check the digilent site for the "The Spartan-3 Starter Board". Its in the list below the Nexys-2.
I would not recomment the Nexys-2 as it uses Dynamic RAM for which there is no support in the analyzer yet. (It is uncertain if there ever will be full support, because DRAM is usually a lot slower than the SRAM.)
nagio (Sun, 22 Jun 2008):
Hi, anyone tried the Spartan 3E Starter Kit version with success? The client can't connect to the board. I'm using a RS232 to USB converter, could this be a problem?
Hi, anyone tried the Spartan 3E Starter Kit version with success? The client can't connect to the board. I'm using a RS232 to USB converter, could this be a problem?
Zhane (Thu, 26 Jun 2008):
How do I use this? Do I just add the sources inside the fpga folder into my project and generate the file?
Im geting error with synthesizing =( Im using the Spartan 3E starter kit
How do I use this? Do I just add the sources inside the fpga folder into my project and generate the file?
Im geting error with synthesizing =( Im using the Spartan 3E starter kit
Daniel (Mon, 30 Jun 2008):
Hi Micha,
What do you think about the SPARTAN 3A Board ? Thats a new development board, which just costs around 40 US$. If an adaption to that board would be possible, it would be perfect.
Any ideas?
cheers,
Daniel
Hi Micha,
What do you think about the SPARTAN 3A Board ? Thats a new development board, which just costs around 40 US$. If an adaption to that board would be possible, it would be perfect.
Any ideas?
cheers,
Daniel
Micha (Thu, 3 Jul 2008):
@nagio:
I'm using a RS232 to USB converter myself without any problems. Have you tried lowering the transfer rate?
@Zhane:
Did you adjust the device settings for your board? Did you add the ucf file too? What is the error message you are getting?
@Daniel:
This board has the same problem as all the newer ones: it uses slow (DDR) SDRAM instead of fast SRAM. There is no SDRAM support built into the analyzer, so you would be limited to the FPGA internal BRAM.
Apart from this I cannot tell you if the 3E version (which uses BRAM) will work on a 3A board.
@nagio:
I'm using a RS232 to USB converter myself without any problems. Have you tried lowering the transfer rate?
@Zhane:
Did you adjust the device settings for your board? Did you add the ucf file too? What is the error message you are getting?
@Daniel:
This board has the same problem as all the newer ones: it uses slow (DDR) SDRAM instead of fast SRAM. There is no SDRAM support built into the analyzer, so you would be limited to the FPGA internal BRAM.
Apart from this I cannot tell you if the 3E version (which uses BRAM) will work on a 3A board.
nagio (Sat, 5 Jul 2008):
yes, but the result is always the same. I've tested the RS232 connection between the board and the laptop using the examples on xilinx website and they works so I don't think the problem lies in the converter.
yes, but the result is always the same. I've tested the RS232 connection between the board and the laptop using the examples on xilinx website and they works so I don't think the problem lies in the converter.
Micha (Sun, 6 Jul 2008):
Unfortunately I do not have a 3E myself, but it works for others. You might want to try to connect the on-board LEDs to input channels or bits of registers (like trigger mask or speed) to see if the analyzer is running at all.
In the offical analyzer package for the regular starter kit the serial rx & tx are also connected to LEDs. If thats not the case for the 3E by default, you should connect those too to see if there is any activity.
Also make sure you are using the client that comes with the modified package, because the regular client does not support RLE.
Unfortunately I do not have a 3E myself, but it works for others. You might want to try to connect the on-board LEDs to input channels or bits of registers (like trigger mask or speed) to see if the analyzer is running at all.
In the offical analyzer package for the regular starter kit the serial rx & tx are also connected to LEDs. If thats not the case for the 3E by default, you should connect those too to see if there is any activity.
Also make sure you are using the client that comes with the modified package, because the regular client does not support RLE.
Hermann Dum (Mon, 7 Jul 2008):
Dear Michael Poppitz,
I tried Your logic analyzer with my newly arrived Spartan3E Starter Board,
it works really fine (WebPack 9.2i). Congratulations for your clearly structured sources.
There are just some little problems left:
1. I am using serial port DCE with a USB-Serial Converter (DA-70145- Rev 2.0 from Digitus).
On my desktop PC it installed as a "Motorola Comp Modem" (USB-Serial Controller) and everything works fine.
On my Laptop PC it installed as a "Prolific USB-to-Serial Comm Port" (USB-Serial Controller) and it works fine with Hyperterm
and my FPGA UARTS but not with your Client. Baudrate, Handshale etc is double checked. - Any Suggestion for debugging?
(Device Id returned is 0x0; device not found)
2. Are there any works done for a glitch detector? I think I would like to have one.
3. Do you know if anybody has written a User Manual for your analyzer?
Yours
DI Hermann Dum
HTBL Hollabrunn
Dear Michael Poppitz,
I tried Your logic analyzer with my newly arrived Spartan3E Starter Board,
it works really fine (WebPack 9.2i). Congratulations for your clearly structured sources.
There are just some little problems left:
1. I am using serial port DCE with a USB-Serial Converter (DA-70145- Rev 2.0 from Digitus).
On my desktop PC it installed as a "Motorola Comp Modem" (USB-Serial Controller) and everything works fine.
On my Laptop PC it installed as a "Prolific USB-to-Serial Comm Port" (USB-Serial Controller) and it works fine with Hyperterm
and my FPGA UARTS but not with your Client. Baudrate, Handshale etc is double checked. - Any Suggestion for debugging?
(Device Id returned is 0x0; device not found)
2. Are there any works done for a glitch detector? I think I would like to have one.
3. Do you know if anybody has written a User Manual for your analyzer?
Yours
DI Hermann Dum
HTBL Hollabrunn
Frank (Mon, 7 Jul 2008):
Hi,
i have a Digitus (includes Prolific chip) USB-RS232 converter, too. It works fine but not with the original MS drivers. So, how to get it running: goto http://www.ftdichip.com/Resources/Utilities.htm and load the "Microsoft USBView" tool. Check with this tool which plXXXX chip is in your USB-RS232 converter. Then goto http://www.prolific.com.tw/eng/Download-2.asp?ID=17 and load the driver for your chipset and install it. Then the converter should work.
regards,
Frank
Hi,
i have a Digitus (includes Prolific chip) USB-RS232 converter, too. It works fine but not with the original MS drivers. So, how to get it running: goto http://www.ftdichip.com/Resources/Utilities.htm and load the "Microsoft USBView" tool. Check with this tool which plXXXX chip is in your USB-RS232 converter. Then goto http://www.prolific.com.tw/eng/Download-2.asp?ID=17 and load the driver for your chipset and install it. Then the converter should work.
regards,
Frank
Zhane (Thu, 10 Jul 2008):
any tutorial on how to set the triggers? Ive managed to make it work..but im clueless with how to set the triggers
any tutorial on how to set the triggers? Ive managed to make it work..but im clueless with how to set the triggers
nagio (Sun, 13 Jul 2008):
thanks, my problem was the version of the client software I was using, I've found a precompiled binary for the spartan 3E board and it works
thanks, my problem was the version of the client software I was using, I've found a precompiled binary for the spartan 3E board and it works
Neoral (Thu, 17 Jul 2008):
How can I program the spartan 3E board using the logic analyzer code to output at the monitor directly using the VGA port of the board?
PLEASE HELP...
How can I program the spartan 3E board using the logic analyzer code to output at the monitor directly using the VGA port of the board?
PLEASE HELP...
scope (Mon, 21 Jul 2008):
Have you tried using the Digilent Port Communications Utility to communicate directly with the FPGA without needing a serial to USB converter? I have researching the possibility of swapping the RS232 module for a USB module but as I have no knowledge of JAVA I can't modify your code and would thus require that I create entirely new graphing/analyzing software.
Have you tried using the Digilent Port Communications Utility to communicate directly with the FPGA without needing a serial to USB converter? I have researching the possibility of swapping the RS232 module for a USB module but as I have no knowledge of JAVA I can't modify your code and would thus require that I create entirely new graphing/analyzing software.
Jeff Epler (Tue, 22 Jul 2008):
I found that the digilentinc product "S3BOARD" works with the logic analyzer. (I recompiled but I'm not sure if this is necessary)
I may have encountered a bug: I selected 200MHz sample rate and only enabled one channel bank. I got my sampled signal interspersed with "0"s. When I sampled at 200MHz and selected two banks, I got the results I expected. Sampling at any other rate than 200MHz did not have this effect.
More on my first experiences with the logic analyzer at http://emergent.unpy.net/01216696167
I found that the digilentinc product "S3BOARD" works with the logic analyzer. (I recompiled but I'm not sure if this is necessary)
I may have encountered a bug: I selected 200MHz sample rate and only enabled one channel bank. I got my sampled signal interspersed with "0"s. When I sampled at 200MHz and selected two banks, I got the results I expected. Sampling at any other rate than 200MHz did not have this effect.
More on my first experiences with the logic analyzer at http://emergent.unpy.net/01216696167
Neoral (Fri, 25 Jul 2008):
Thanks a lot...
I will try to do it...
I am very interested in it...
I will try to make the hardware of it first...
So that I will be motivated to do it...
Thanks a lot...
I will try to do it...
I am very interested in it...
I will try to make the hardware of it first...
So that I will be motivated to do it...
Neoral (Fri, 1 Aug 2008):
I synthesized the program then it is ok...
I implemented the program then it went bad, itleaves an error...
what seems to be wrong in the program?
Can someone in here help me?
Just want to know where is the main cause of it
I synthesized the program then it is ok...
I implemented the program then it went bad, itleaves an error...
what seems to be wrong in the program?
Can someone in here help me?
Just want to know where is the main cause of it
Torlus (Sun, 9 Nov 2008):
Very nice project. I was looking for an affordable logic analyzer for my emulation-related stuff, and I was thinking about using my Starter Board for this purpose. That's exactly what you did, and in a very nice way. Congratulations for the project itself, and the extensive amount of documentation you provided.
Regards,
Greg
Very nice project. I was looking for an affordable logic analyzer for my emulation-related stuff, and I was thinking about using my Starter Board for this purpose. That's exactly what you did, and in a very nice way. Congratulations for the project itself, and the extensive amount of documentation you provided.
Regards,
Greg
Anthony (Sun, 18 Jan 2009):
I love your work. I have the hardware and software all functioning. I have found that the zoom function does not work very well. When zooming in (and out), the currently viewed part of the waveform is moved out of the visible window. It would seem that the window position needs to be manually updated to compensate for the zoom factor.
I am new to Java and relatively new to OOP, but I was trying to work on the code using Eclipse. I can not seem to find a way to interact with a viewport object to change the visible region. I would love to do a little work on this and then give you the final result. Do you have any pointers for me? E.G. Would making the Diagram object extend JScrollPane rather than JContainer be useful? I have tried all sorts of xxx.getParent() to get a useful viewport without any luck. Since I am very new to Java, I have run out of ideas.
I love your work. I have the hardware and software all functioning. I have found that the zoom function does not work very well. When zooming in (and out), the currently viewed part of the waveform is moved out of the visible window. It would seem that the window position needs to be manually updated to compensate for the zoom factor.
I am new to Java and relatively new to OOP, but I was trying to work on the code using Eclipse. I can not seem to find a way to interact with a viewport object to change the visible region. I would love to do a little work on this and then give you the final result. Do you have any pointers for me? E.G. Would making the Diagram object extend JScrollPane rather than JContainer be useful? I have tried all sorts of xxx.getParent() to get a useful viewport without any luck. Since I am very new to Java, I have run out of ideas.
Frank (Mon, 19 Jan 2009):
Hi,
did you use the latest sources from http://sourceforge.net/projects/jlac/ ? It has cursors with a "goto" function included. This could be used as a base for setting the viewport position after zooming.
Br,
Frank
Hi,
did you use the latest sources from http://sourceforge.net/projects/jlac/ ? It has cursors with a "goto" function included. This could be used as a base for setting the viewport position after zooming.
Br,
Frank
Derek (Wed, 28 Jan 2009):
Hi,
First off Micha, thanks so much for this wonderful tool! I'm looking forward to working with, and extending it.
Secondly for those out there who see good "bang for your buck" on the NEXSYS2 board, I was able to get the software to work with 20khz and 100khz signals with the NEXSYS2 board. I used the code from "Spartan 3E: Experimental Version for New Spartan 3E Starter Kit" modifying only the .ucf for the fpga pin assignments. I do not have a signal generator that is much faster than that at this time, so I cannot comment on the performance at higher speeds, but I'm assuming it should be okay.
The RLE included in the above code gives me garbage - but I'm not worried about that feature right now.
Hi,
First off Micha, thanks so much for this wonderful tool! I'm looking forward to working with, and extending it.
Secondly for those out there who see good "bang for your buck" on the NEXSYS2 board, I was able to get the software to work with 20khz and 100khz signals with the NEXSYS2 board. I used the code from "Spartan 3E: Experimental Version for New Spartan 3E Starter Kit" modifying only the .ucf for the fpga pin assignments. I do not have a signal generator that is much faster than that at this time, so I cannot comment on the performance at higher speeds, but I'm assuming it should be okay.
The RLE included in the above code gives me garbage - but I'm not worried about that feature right now.
Dave (Fri, 6 Feb 2009):
Thanks for the impressively well written and understandable RTL.
I was wondering, have you considered implementing the Sump Analyzer on larger FPGAs and use it as a means to monitor internal signals much like Altera's Signal Tap II Logic Analyzer? The logic is probably small enough to fit along side an existing design in a Altera DE1/DE2.
Thanks for the impressively well written and understandable RTL.
I was wondering, have you considered implementing the Sump Analyzer on larger FPGAs and use it as a means to monitor internal signals much like Altera's Signal Tap II Logic Analyzer? The logic is probably small enough to fit along side an existing design in a Altera DE1/DE2.
Mike Perks (Sun, 15 Feb 2009):
I have written a user guide for the current Logic Analyzer client that you may find useful - see oakmicros.com/content/downloads/View-document/Logic-Analyzer-User-Guide.html
I also sell a logic level interface board called the omla32 that allows up to 5V for the 32 inputs and optional external clock. See oakmicros.com/content/omla32-Logic-Analyzer-Interface-Card.html
I have written a user guide for the current Logic Analyzer client that you may find useful - see oakmicros.com/content/downloads/View-document/Logic-Analyzer-User-Guide.html
I also sell a logic level interface board called the omla32 that allows up to 5V for the 32 inputs and optional external clock. See oakmicros.com/content/omla32-Logic-Analyzer-Interface-Card.html
Linus (Tue, 17 Feb 2009):
I just received my Digilent starter kit and had this Logic Analyzer work
in just a few minutes! I am really impressed to say the least ;0).
I plan to change the onboard SRAMs with two 2Mx 8 IS64WV20488BLL
http://www.issi.com/pdf/61-64WV20488.pdf
I do not really need 32 channels and I think a 16 channels with a 2M buffer
is more useful after I do some tinkering with the VHDL model.
Great Work!
I just received my Digilent starter kit and had this Logic Analyzer work
in just a few minutes! I am really impressed to say the least ;0).
I plan to change the onboard SRAMs with two 2Mx 8 IS64WV20488BLL
http://www.issi.com/pdf/61-64WV20488.pdf
I do not really need 32 channels and I think a 16 channels with a 2M buffer
is more useful after I do some tinkering with the VHDL model.
Great Work!
Mike Perks (Mon, 23 Feb 2009):
Some comments for Linus.
I think you will find that the extra address line you need is not connected to the FPGA and you will need to solder in something yourself.
Also there is a version of the FPGA code that does a run length encoding (RLE) of the data to reduce its size in memory. This may be suitable for your needs. The Java client for RLE needs a bit more work and is available from http://sourceforge.net/projects/jlac
Some comments for Linus.
I think you will find that the extra address line you need is not connected to the FPGA and you will need to solder in something yourself.
Also there is a version of the FPGA code that does a run length encoding (RLE) of the data to reduce its size in memory. This may be suitable for your needs. The Java client for RLE needs a bit more work and is available from http://sourceforge.net/projects/jlac
Kevin (Mon, 23 Feb 2009):
I would think that I could sample 5v signals by using 3.3v Zeners instead of building the add-on board? I.E. Each input would have a resistor and then a zener which would give a max of 3.3v...
I would think that I could sample 5v signals by using 3.3v Zeners instead of building the add-on board? I.E. Each input would have a resistor and then a zener which would give a max of 3.3v...
Linus (Thu, 26 Feb 2009):
@ Mike Perks
Thanks for the heads up Mike. ;O)
I plan to remove both of the stock SRAMS and replace it
with just 1 BIG SRAM. This will give me enough I/Os for
the wider address lines.
I did not check the original VHDL code yet, I actually used
the ones on your site hehehe.
Btw, I will be ordering your add-on board ;O)
B.R.
@ Mike Perks
Thanks for the heads up Mike. ;O)
I plan to remove both of the stock SRAMS and replace it
with just 1 BIG SRAM. This will give me enough I/Os for
the wider address lines.
I did not check the original VHDL code yet, I actually used
the ones on your site hehehe.
Btw, I will be ordering your add-on board ;O)
B.R.
Christian (Tue, 10 Mar 2009):
I am searching for a cheap compatible board with SRAM(!).
Whats about the Zefant LC3E Board?
It contains a XC3S??? (??? = 250.000 macro cells), with 4MB SRAM and 32 MB Flash.
In germany it costs less than 100EUR.
The
http://shop.trenz-electronic.de/catalog/productinfo.php?productsid=172
Christian
I am searching for a cheap compatible board with SRAM(!).
Whats about the Zefant LC3E Board?
It contains a XC3S??? (??? = 250.000 macro cells), with 4MB SRAM and 32 MB Flash.
In germany it costs less than 100EUR.
The
http://shop.trenz-electronic.de/catalog/productinfo.php?productsid=172
Christian
Christian (Wed, 11 Mar 2009):
Sorry, it is a failure in the data:
only 4MBit SRAM = 512kByte; and 32MBit Flash = 4MByte (!)
Christian
Sorry, it is a failure in the data:
only 4MBit SRAM = 512kByte; and 32MBit Flash = 4MByte (!)
Christian
Joep (Sat, 14 Mar 2009):
Hi,
I just received my digilent board and intended to use my arm-usb-tiny from Olimex to program. But the xilinx webpack does not seem to support this jtag interface. I did manage to have openocd report a two-device chain, so I presume the hardware is connected correctly. But that's where I ended.
Can somebody please help me on configuring openocd (or an other way) to program the board?
Tnx,
Joep
Hi,
I just received my digilent board and intended to use my arm-usb-tiny from Olimex to program. But the xilinx webpack does not seem to support this jtag interface. I did manage to have openocd report a two-device chain, so I presume the hardware is connected correctly. But that's where I ended.
Can somebody please help me on configuring openocd (or an other way) to program the board?
Tnx,
Joep
Ashok (Wed, 18 Mar 2009):
Hi!
I m a student of B.tech 3rd year and we have been asked do a projejt on VHDL and i m not getting what sort of project can be done in this.
So, I shall be highly obliged to u if u can suggest me some project.
Thank you.
Hi!
I m a student of B.tech 3rd year and we have been asked do a projejt on VHDL and i m not getting what sort of project can be done in this.
So, I shall be highly obliged to u if u can suggest me some project.
Thank you.
MikePerks (Sun, 22 Mar 2009):
The "omla32" logic level interface board I announced here just over a month ago has been very popular. I am happy to report that they are in stock again. See http://oakmicros.com/content/omla32-Logic-Analyzer-Interface-Card.html
I also have written a user guide for the current Logic Analyzer client that you may find useful - see http://oakmicros.com/content/downloads/View-document/Logic-Analyzer-User-Guide.html
The "omla32" logic level interface board I announced here just over a month ago has been very popular. I am happy to report that they are in stock again. See http://oakmicros.com/content/omla32-Logic-Analyzer-Interface-Card.html
I also have written a user guide for the current Logic Analyzer client that you may find useful - see http://oakmicros.com/content/downloads/View-document/Logic-Analyzer-User-Guide.html
siva (Thu, 9 Apr 2009):
hi
i am 3rd yr student. can some one tell the concept of how sampling is done in this project.
hi
i am 3rd yr student. can some one tell the concept of how sampling is done in this project.
siva (Thu, 9 Apr 2009):
hi. i am a 3rd yr student. pl help to understand the concept of sampling done in this project
hi. i am a 3rd yr student. pl help to understand the concept of sampling done in this project
Levas (Sat, 25 Apr 2009):
I tested this project using Altera Cyclone chip (Nios Dev board). The only problematic place is serial link. As I don't have RS232 on my computer I was using FTDI chip (ft232). I've tested several transmission speeds but only low speed ones are usable. At high speed only small part of data are transmited then system crashes. I don't this it is hardware problem as I transfered data from other projects using save chip at very high speed. I think it is problem in java software.
I wrote small article about it in my blog (sorry, still no english translation).
http://www.vabolis.lt/2008/03/26/loginis-analizatorius/
I tested this project using Altera Cyclone chip (Nios Dev board). The only problematic place is serial link. As I don't have RS232 on my computer I was using FTDI chip (ft232). I've tested several transmission speeds but only low speed ones are usable. At high speed only small part of data are transmited then system crashes. I don't this it is hardware problem as I transfered data from other projects using save chip at very high speed. I think it is problem in java software.
I wrote small article about it in my blog (sorry, still no english translation).
http://www.vabolis.lt/2008/03/26/loginis-analizatorius/
RV (Sat, 25 Apr 2009):
Hi,
great work ! I tested the file for a Spartan 3E demo board, without any problem.
The above problem with serial port could be the XON/XOFF.
Hi,
great work ! I tested the file for a Spartan 3E demo board, without any problem.
The above problem with serial port could be the XON/XOFF.
Jon Nall (Tue, 12 May 2009):
I had to add a synchronizer for the rx pin on the Nexys2 board. Otherwise I observed metastability issues.
I had to add a synchronizer for the rx pin on the Nexys2 board. Otherwise I observed metastability issues.
Krishna Neupane (Tue, 30 Jun 2009):
Dear Sir, Could you please give me the idea of the overview of this project...i am a bit confused.I want to know what is the use of FPGA here?..can the java client like be made in Matlab..if so how?Could you please send me the details of the project?i will be very glad.
Thank you.
my email address:\"theneupane@hotmail.com\"
Dear Sir, Could you please give me the idea of the overview of this project...i am a bit confused.I want to know what is the use of FPGA here?..can the java client like be made in Matlab..if so how?Could you please send me the details of the project?i will be very glad.
Thank you.
my email address:\"theneupane@hotmail.com\"
charlie (Thu, 2 Jul 2009):
I managed to get it running on a Spartan 3 with xc3s1000, omla interface and ISE 11.2, runs at 115K just fine.
cheers!
I managed to get it running on a Spartan 3 with xc3s1000, omla interface and ISE 11.2, runs at 115K just fine.
cheers!
Krishna (Thu, 2 Jul 2009):
Sir,Can I get the documentation of the project.I need it urgent.I will be grateful to you for this approval.
email:theneupane@hotmail.com
Sir,Can I get the documentation of the project.I need it urgent.I will be grateful to you for this approval.
email:theneupane@hotmail.com
Chris (Thu, 2 Jul 2009):
Dear sir,could you please send me the documentation of the project...i will be very grateful to you for this?
email:\"theneupane@hotmail.com
Dear sir,could you please send me the documentation of the project...i will be very grateful to you for this?
email:\"theneupane@hotmail.com
Arun P (Thu, 9 Jul 2009):
Hi, I have done a project on the same platform xc3s400 for image edge detection. We did it using a college FPGA kit, and I am wondering how much it would cost to setup a development environment.
Hi, I have done a project on the same platform xc3s400 for image edge detection. We did it using a college FPGA kit, and I am wondering how much it would cost to setup a development environment.
Jack (Tue, 21 Jul 2009):
The \"Sump\" Logic Analyzer is also running on a completely Open Source FPGA board called \"Butterfly Light\". Eagle schematic and board files are available for download as well as a precompiled version of the very latest Java Client which was checked out from CVS. For those who are not interested in building their own boards there are assembled boards available for purchase.
Screencasts on usage of the Logic Analyzer are available and more are on the way, so keep checking back.
Project page is http://www.gadgetfactory.net/gf/project/lax/.
The \"Sump\" Logic Analyzer is also running on a completely Open Source FPGA board called \"Butterfly Light\". Eagle schematic and board files are available for download as well as a precompiled version of the very latest Java Client which was checked out from CVS. For those who are not interested in building their own boards there are assembled boards available for purchase.
Screencasts on usage of the Logic Analyzer are available and more are on the way, so keep checking back.
Project page is http://www.gadgetfactory.net/gf/project/lax/.
Andrzej (Wed, 5 Aug 2009):
Just a quick note - the Spartan 3E version of the analyzer works great on the cheap avnet spartan 3A board (SRAM-less). The only adjustments required are (obviously) the pinouts and clock setting.
Just a quick note - the Spartan 3E version of the analyzer works great on the cheap avnet spartan 3A board (SRAM-less). The only adjustments required are (obviously) the pinouts and clock setting.
jiggly67 (Thu, 6 Aug 2009):
Andrzej,
Could you please post the VHDL source for the 3A? or send it to me at jiggly67@yahoo.com
Thx.
Andrzej,
Could you please post the VHDL source for the 3A? or send it to me at jiggly67@yahoo.com
Thx.
pbltd (Thu, 6 Aug 2009):
Hi Andrzej,
could you please post the VHDL source for the Avnet Spartan 3A board or send it to me: bauerp@hotmail.com
Cheers!
Hi Andrzej,
could you please post the VHDL source for the Avnet Spartan 3A board or send it to me: bauerp@hotmail.com
Cheers!
rfhn (Fri, 21 Aug 2009):
Are there any limitation in using the Avnet 3a board
Please also send the the VHDL source to me
rfhn@hotmail.com
Thanks
Are there any limitation in using the Avnet 3a board
Please also send the the VHDL source to me
rfhn@hotmail.com
Thanks
RFHN (Fri, 21 Aug 2009):
There are many boards suggested as a base for the Logic Analyzer. Since I know very little of these products can someone help me by posting the #samples, Sample Rate, and if appropriate the # of channels each of the following support
Gadget:butterfy
Spartan 3
Spartan 3A (SRAM-less).
Spartan 3E 1Mb?
NEXSYS2
Thanks
There are many boards suggested as a base for the Logic Analyzer. Since I know very little of these products can someone help me by posting the #samples, Sample Rate, and if appropriate the # of channels each of the following support
Gadget:butterfy
Spartan 3
Spartan 3A (SRAM-less).
Spartan 3E 1Mb?
NEXSYS2
Thanks
Andi (Thu, 17 Sep 2009):
Hallo,
Ich will mir Deinen LA mal bauen.
Das Spartan 3 Starter Kit gibt es in 2 Varianten.
Eins mit 200k und eins mit 1000k Gates.
Welches brauche ich?
Ich habe noch nix in FPGA gemacht...
Danke
Gruss Andi
Hallo,
Ich will mir Deinen LA mal bauen.
Das Spartan 3 Starter Kit gibt es in 2 Varianten.
Eins mit 200k und eins mit 1000k Gates.
Welches brauche ich?
Ich habe noch nix in FPGA gemacht...
Danke
Gruss Andi
Pedro Salazar (Wed, 14 Oct 2009):
Such a really great job this logic analyzer.
Michael I am studing an expertise in embedded system. The project I will perform is a basic logic analyzer. I would like to see if you could give a guidance. In this way, which information do you recommend me to read about first and so on. I\'ll appreciate your help.
Thank you in advance.
P.D. My email: salazarortega@hotmail.com
Such a really great job this logic analyzer.
Michael I am studing an expertise in embedded system. The project I will perform is a basic logic analyzer. I would like to see if you could give a guidance. In this way, which information do you recommend me to read about first and so on. I\'ll appreciate your help.
Thank you in advance.
P.D. My email: salazarortega@hotmail.com
Andrzej (Sat, 17 Oct 2009):
@everyone requesting the Spartan 3A version:
Sorry for the obviously late response, I haven\'t been checking this page recently. I\'ve put a tarball here: http://kuku.eu.org/s3ala/s3a-la.tar.bz2
@everyone requesting the Spartan 3A version:
Sorry for the obviously late response, I haven\'t been checking this page recently. I\'ve put a tarball here: http://kuku.eu.org/s3ala/s3a-la.tar.bz2
Glenn Holt (Fri, 30 Oct 2009):
Thanks Andrzej, it works great with the AvNet S3A board. I think I\'ll try to re-spin it to reach 100MHz. It looks like
50MHz is the max sampling rate currently (78MHz in the Xilinx timing summary).
Thanks Andrzej, it works great with the AvNet S3A board. I think I\'ll try to re-spin it to reach 100MHz. It looks like
50MHz is the max sampling rate currently (78MHz in the Xilinx timing summary).
lekernel (Sun, 1 Nov 2009):
@Micha: DDR SDRAM is not slow, you just need to write a proper controller. It\'s a lot more complex than SRAM/BRAM though.
See http://www.milkymist.org/doc/hpdmc.pdf
@Micha: DDR SDRAM is not slow, you just need to write a proper controller. It\'s a lot more complex than SRAM/BRAM though.
See http://www.milkymist.org/doc/hpdmc.pdf
FPGA-guy (Wed, 4 Nov 2009):
The logic analyzer and it\'s open protocol are very interesting, however, Java ruins the thing as far as I\'m concerned. (slow, clunky, unreliable, huge, dependant on an ever changing runtime executable, etc ...) A standalone C (or any compilable language you want) program would be a vastly superior alternative.
The logic analyzer and it\'s open protocol are very interesting, however, Java ruins the thing as far as I\'m concerned. (slow, clunky, unreliable, huge, dependant on an ever changing runtime executable, etc ...) A standalone C (or any compilable language you want) program would be a vastly superior alternative.
Likewise (Wed, 18 Nov 2009):
Java is compilable into native machine code by GCJ (in GCC), at least for some platforms.
Java is compilable into native machine code by GCJ (in GCC), at least for some platforms.
Jack Gassett (Mon, 23 Nov 2009):
Hello,
We are working on a low cost ($30-40) Open Source implementation of the Sump Logic Analyzer based on the Spartan 3E. All help and input is greatly appreciated, come take a look and help us get this project completed.
Please join us at http://www.gadgetfactory.net/gf/project/butterflylogic/
Thank you,
Jack.
Hello,
We are working on a low cost ($30-40) Open Source implementation of the Sump Logic Analyzer based on the Spartan 3E. All help and input is greatly appreciated, come take a look and help us get this project completed.
Please join us at http://www.gadgetfactory.net/gf/project/butterflylogic/
Thank you,
Jack.
boki (Mon, 14 Dec 2009):
Hi,
Could sampling speed be much higher? For example using four 100MHz clocks each phase shifted with +90, so we have clock1 PS 0, clock2 PS90, clock2 PS180, clock2 PS270 and we have 4 memories to write data from each clock and 4 different process which write data to memory?Thus we can get 4 samples per one period?
boki
Hi,
Could sampling speed be much higher? For example using four 100MHz clocks each phase shifted with +90, so we have clock1 PS 0, clock2 PS90, clock2 PS180, clock2 PS270 and we have 4 memories to write data from each clock and 4 different process which write data to memory?Thus we can get 4 samples per one period?
boki
Laurent Gauch (Tue, 12 Jan 2010):
Hello boki,
You could imagine to use 4 phase shifted 90 degreed only if you want to sample signals in the FPGA. If you want to use PIO (IO port, sampling external signals) you have to use dual rate flip-flip architechture only.
Regards,
Laurent
http://www.amontec.com
Amontec JTAGkey-2 High-Speed Generic USB JTAG adapter.
Hello boki,
You could imagine to use 4 phase shifted 90 degreed only if you want to sample signals in the FPGA. If you want to use PIO (IO port, sampling external signals) you have to use dual rate flip-flip architechture only.
Regards,
Laurent
http://www.amontec.com
Amontec JTAGkey-2 High-Speed Generic USB JTAG adapter.
fishfish (Thu, 21 Jan 2010):
For anyone else trying to compile for an S3Board with ISE 11.1, change d9 to n8 in la.ucf to get rid of the \"This will not allow the use of the fast path between the IO and the Clock buffer\" error. From what I can tell from the datasheets, this is the only global clock site able to be connected to a clock mux with t9 which isn\'t used for something else on the board.
For anyone else trying to compile for an S3Board with ISE 11.1, change d9 to n8 in la.ucf to get rid of the \"This will not allow the use of the fast path between the IO and the Clock buffer\" error. From what I can tell from the datasheets, this is the only global clock site able to be connected to a clock mux with t9 which isn\'t used for something else on the board.
Laurent Gauch Amontec (Mon, 25 Jan 2010):
Hi Fishfish,
What version are you using. The v0.8 synchronize exClock with xtalClock, so there are no need of GCLK on exClock.
Laurent
http://www.amontec.com
Hi Fishfish,
What version are you using. The v0.8 synchronize exClock with xtalClock, so there are no need of GCLK on exClock.
Laurent
http://www.amontec.com
Manuel (Wed, 27 Jan 2010):
Hi, tried to implement the design on an S3Board with 1000k gates with ISE10.1 and ISE11.4. With the exception of the \"CLOCKDEDICATEDROUTE = FALSE\" for the exClock I have not changed anything. Unfortunately nothing works - I cann see the signals on the 7Seg leds but when I press capture the signals went off and I only get zeros as a result.... Any Ideas?
Hi, tried to implement the design on an S3Board with 1000k gates with ISE10.1 and ISE11.4. With the exception of the \"CLOCKDEDICATEDROUTE = FALSE\" for the exClock I have not changed anything. Unfortunately nothing works - I cann see the signals on the 7Seg leds but when I press capture the signals went off and I only get zeros as a result.... Any Ideas?
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